1. Field of the Invention
The present invention relates to a shallow trench isolation (“STI”) structure and fabricating methods for the same. In particular, the present invention relates to an STI structure that can improve an operating speed of a transistor and a latch-up characteristic by changing the STI structure and fabricating methods thereof.
2. Description of Related Art
FIGS. 1a–e illustrate the process steps according a conventional STI fabricating method. In this conventional method, a pad oxide layer 2 is grown on a silicon substrate 1. A nitride layer 3 is then deposited on the pad oxide layer 2 as shown in FIG. 1a. The nitride layer 3, the pad oxide layer 2, and the silicon substrate 1 are then etched to form the trench, as shown in FIG. 1b. A thermal oxide layer 5 is then grown on the etched surface etched, as shown in FIG. 1c. An oxide layer 6 is then deposited on the thermal oxide layer 5 and the nitride layer 3 by atmospheric pressure chemical vapor deposition (“APCVD”). A densification process is then performed. Next, referring to FIG. 1d and FIG. 1e, chemical mechanical polishing (“CMP”) is then performed, and, finally, the nitride layer 3 is removed using an HF wet etch to complete an STI forming process. Subsequently, a MOS transistor is then fabricated.
The MOS transistor fabricated by the above-described process may have a parasitic source/drain junction capacitor due to structural features of the structure. As a result, the operating speed of a transistor slows due to an increase in the gate RC delay. Furthermore, a junction between the bottom of source/drain and P-well or N-well may form, which can cause an IC chip to consume a large amount of electric power due to increased junction leakage.
Korean Patent Publication No. 10-1999-0061132 discloses a method for ensuring a process margin by insulating between cells using a silicon on insulator (“SOI”) structure and a STI structure to apply a back bias. The method includes performing an oxygen ion implantation for a P-type semiconductor substrate so that the oxygen ion is positioned on a desired depth. A trench is formed on the substrate with a SOI structure having a buried oxide layer formed by a thermal oxidation process and a silicon layer. An STI structure is formed to insulate between a cell in the P-type semiconductor substrate and a cell in the silicon layer so as to apply back bias This process, however, has settled a problem that the insulated layer is floated on the top of the buried oxide.
FIGS. 2a–2e illustrate the process steps according to the fabricating method described in the above-mentioned Korean patent publication. A buried oxide layer 11 and a silicon layer 12 are formed on a semiconductor substrate 10, as shown in FIG. 2a. A trench 13 for making an STI is then formed by etching the silicon layer 12 and the buried oxide layer 11, as shown in FIG. 2b. A spacer 14 is then formed on the inside walls of the trench 13, as shown in FIG. 2c. A field-stop impurity area 15 is then formed in the substrate 10 under the trench 13, as shown in FIG. 2d. An insulating layer 16 is then formed to fill the trench, as shown in FIG. 2e. 
This process forms a silicon layer 12 instead of a nitride layer on the buried oxide layer, and provides no clear means for forming the spacer 14. In addition, the spacer 14 is buried by the insulating layer 16, thereby increasing the probability of void formation. As such, this process cannot substantially reduce the source/drain junction capacitance and junction leakage. Furthermore, it cannot improve the operating speed of the transistor and the latch-up characteristic.